The present invention relates generally to power regulation. More specifically, but without limitation thereto, the present invention relates to regulating power in integrated circuits having circuit components connected to power buses by conductors subject to significant voltage drops.
In a conventional method for distributing power across a low-cost peripherally bonded chip, power and ground are connected to bond pads located along the four edges of the die and then routed horizontally on metal buses to the remainder of the chip. The power and ground pads are typically tied orthogonally to global metal buses that are part of power and ground rings circling the outside of the chip to provide separate supplies for the I/O pads and to tie together common supply pads. Typically there are more than two supply rings to provide separate supplies for the I/O pads and circuit components on the inside of the chip. The supply rings are connected to a set of alternating power and ground buses that carry power across the chip. These buses use a substantial fraction of the area of the top metal layer to maintain IR drops (voltage drops due to current flowing through the bus resistance) within a few percent of the voltage rail. The remaining area of the top metal layer between the buses is left for wiring tracks for global signals such as the clock signal. The global power buses feed a set of local power buses that carry power to circuit components inside the chip circuit.
With scaling of minimum feature size and accompanying increases in transistor count, the interconnect wire current densities and resistance per unit length increase due to shrinking cross-sections. These effects are especially pronounced in the power distribution network of scaled supply voltages, increasing chip currents, and increasing chip size, where IR drops become a larger fraction of the supply voltage. The increased IR drops limit performance characteristics and may also cause logic failures. As IR drops across power and ground pads become larger fractions of the supply voltage, the I/O counts for the peripherally bonded chip power supply are determined by the maximum IR drop that may be tolerated along the pad. The Process Integration and Devices section of the 1997 National Technology Roadmap for Semiconductors (NTRS) warns that metal consumption by power, ground, and clock distribution networks will increase with scaling. The dependency of size and cycle time performance of wire limited logic chips on the wiring area requirements of the chip translates directly into longer cycle time, larger chip area, and higher chip and system cost.